2-wire time independent asynchronous communications

Radcliffe, P 2006, 2-wire time independent asynchronous communications, Doctor of Philosophy (PhD), Electrical and Computer Engineering, RMIT University.


Document type: Thesis
Collection: Theses

Attached Files
Name Description MIMEType Size
AVR_BIT_ECHO.zip AVR_BIT_ECHO.zip Click to show the corresponding preview/stream application/zip 13.96KB
AVR_BIT_ECHO_CORRUPT.zip AVR_BIT_ECHO_CORRUPT.zip Click to show the corresponding preview/stream application/zip 15.74KB
AVR_BYTE_ECHO.zip AVR_BYTE_ECHO.zip Click to show the corresponding preview/stream application/zip 17.30KB
DEBUG_PROFORMA_8535.zip DEBUG_PROFORMA_8535.zip Click to show the corresponding preview/stream application/zip 75.82KB
DEBUG_PROFORMA_TINY26.zip DEBUG_PROFORMA_TINY26.zip Click to show the corresponding preview/stream application/zip 96.16KB
PC_DEMO.zip PC_DEMO.zip Click to show the corresponding preview/stream application/zip 37.43KB
Radcliffe.pdf Thesis application/pdf 3.14MB
SIM.zip SIM.zip Click to show the corresponding preview/stream application/zip 2.51MB
Title 2-wire time independent asynchronous communications
Author(s) Radcliffe, P
Year 2006
Abstract Communications both to and between low end microprocessors represents a real cost in a number of industrial and consumer products. This thesis starts by examining the properties of protocols that help to minimize these expenses and comes to the conclusion that the derived set of properties define a new category of communications protocol : Time Independent Asynchronous ( TIA) communications. To show the utility of the TIA category we develop a novel TIA protocol that uses only 2-wires and general IO pins on each host. The protocol is analyzed using the Petri net based STG ( Signal Transition Graph) which is widely use to model asynchronous logic. It is shown that STGs do not accurately model the behavior of software driven systems and so a modified form called STG-FT ( STG For Threads) is developed to better model software systems. A simulator is created to take an STG-FT model and perform a full reachability tree analysis to prove correctness and analyze livelock and deadlock properties. The simulator can also examine the full reachability tree for every possible system state ( the cross product of all sub-system states), and analyze deadlock and livelock issues related to unexpected inputs and unusual situations. Reachability pruning algorithms are developed which decrease the search tree by a factor of approximately 250 million. The 2-wire protocol is implemented between a PC and an Atmel Tiny26 microprocessor, there is also a variant that works between microprocessors. Testing verifies the simulation results including an avoidable livelock condition with data throughput peaking at a useful 50 kilobits/second in both directions. The first practical application of 2-wire TIA is part of a novel debugger for the Atmel Tiny26 microprocessor. The approach can be extended to any microprocessor with general IO pins. TIA communications, developed in this thesis, is a serious contender whenever low end microprocessors must communicate with other processors. Consumer and industrial products may be able to achieve cost saving by using this new protocol.
Degree Doctor of Philosophy (PhD)
Institution RMIT University
School, Department or Centre Electrical and Computer Engineering
Keyword(s) TIA
Time Independent Asynchronous Communications
Petri net
Communications
Asynchronous
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Created: Thu, 09 Jun 2011, 14:11:37 EST by Guy Aron
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