Radiation hard FPGA configuration techniques using silicon on sapphire

Haque, K 2011, Radiation hard FPGA configuration techniques using silicon on sapphire, Masters by Research, Electrical and Computer Engineering, RMIT University.


Document type: Thesis
Collection: Theses

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Title Radiation hard FPGA configuration techniques using silicon on sapphire
Author(s) Haque, K
Year 2011
Abstract  Once entirely the domain of space-borne applications, the effects of high energy charged particles on electronics systems is now also a concern for terrestrial devices. Reconfigurable components such as FPGAs are particularly vulnerable to radiation single event effects (SEU) as they carry a large amount of memory within a relatively small amount of circuit area. This thesis presents a Silicon on Insulator (SOI) based configuration memory system in a radiation hard reconfiguration system. The SOI technology used in this particular work is Silicon on Sapphire, where Sapphire is used as the body insulator. A non-volatile storage cell, able to be manufactured in a standard single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt amplifier which result a final structure that exhibits two unique characteristics enhancing its resistance to radiation. Firstly, it is impossible for a radiation induced event to permanently flip the configuration state. Secondly, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can be very easily detected using a conventional sense amplifier. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self-correcting, or “auto-scrubbing” behavior. While the combination of SOI EEPROM and Schmitt exhibits high intrinsic resistance to radiation induced errors, it is still possible for a sequence of two particle strikes to cause the configuration value to be lost. Estimates are made of the Soft error Rate (SER) performance of the overall configuration memory structure. A trial layout of a configurable Look Up Table (LUT) is presented as an example of how the SOS EEPROM configuration cell would be deployed in a real system.
Degree Masters by Research
Institution RMIT University
School, Department or Centre Electrical and Computer Engineering
Keyword(s) Radiation Hard
SOI EEPROM
Configuration memory
Auto-scrubbing
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Created: Tue, 24 Jul 2012, 17:08:37 EST by Guy Aron
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