Near and sub-threshold NULL convention logic design for low-power digital signal processing applications

Sovani, R 2016, Near and sub-threshold NULL convention logic design for low-power digital signal processing applications, Masters by Research, Electrical and Computer Engineering, RMIT University.


Document type: Thesis
Collection: Theses

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Title Near and sub-threshold NULL convention logic design for low-power digital signal processing applications
Author(s) Sovani, R
Year 2016
Abstract Portable devices such as heart monitors, pacemakers and hearing aids requiring speech frequency filtering, can achieve low power operation if operated with reduced supply voltages near the threshold of their transistor components. However, in this region the effects of Process, Voltage and Temperature (PVT) variations are much more prominent. As a result, low-voltage clocked systems can often require much greater design effort and additional resources to be applied to avoid PVT-related failures, potentially leading to excessive and undesirable design margins. Asynchronous techniques are generally more tolerant to these variations and have been suggested for use in low power, wearable applications. Out of the range of available asynchronous techniques, Null Convention Logic has been shown to be simple to design and robust in the face of PVT variability. Its main disadvantages are that its basic components are bulky and current implementation tools are not optimized for this type of asynchronous design. Further, NCL standard cell libraries are rarely, if ever, available as part of a vendor-supplied process kit for integrated circuit manufacture. Furthermore, Short word-length (SWL) filter systems that operate, for example, on sin- gle bit Sigma-Delta encoded data have also been suggested for low-power and portable systems. Synchronous short word length filters using oversampling of both data and coefficients and operating in this domain have already been shown to be typically more hardware efficient and give better performance than their equivalent multi-bit counter- parts. However, while Sigma-Delta techniques do serve to reduce the overall complexity of the hardware, their use of oversampling to move the quantization noise out of the region of interest results in many more filter stages than in the conventional case. Thus, it is not immediately clear whether the technique will always result in more efficient filter circuits.
Degree Masters by Research
Institution RMIT University
School, Department or Centre Electrical and Computer Engineering
Subjects Signal Processing
Microelectronics and Integrated Circuits
Keyword(s) NULL convention Logic
Short word length devices
Digital signal processing
Asynchronous
FIR
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Created: Wed, 19 Oct 2016, 11:05:23 EST by Keely Chapman
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