A polymorphic hardware platform

A polymorphic hardware platform

Beckett, P 2003, 'A polymorphic hardware platform', in M. Williams (ed.) Proceedings of International Parallel and Distributed Processing Symposium, France, 22-26 April 2003, pp. 1-8.

Document type:	Conference Paper
Collection:	Conference Papers

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Title	A polymorphic hardware platform
Author(s)	Beckett, P
Year	2003
Conference name	International Parallel and Distributed Processing Symposium
Conference location	France
Conference dates	22-26 April 2003
Proceedings title	Proceedings of International Parallel and Distributed Processing Symposium
Editor(s)	M. Williams
Publisher	IEEE
Place of publication	Los Alamitos, California
Start page	1
End page	8
Abstract	In the domain of spatial computing, it appears that platforms based on either reconfigurable datapath units or on hybrid microprocessor/logic cell organizations are in the ascendancy as they appear to offer the most efficient means of providing resources across the greatest range of hardware designs. This paper encompasses an initial exploration of an alternative organization. It looks at the effect of using a very fine-grained approach based on a largely undifferentiated logic cell that can be configured to operate as a state element, logic or interconnect - or combinations of all three. A vertical layout style hides the overheads imposed by reconfigurability to an extent where very fine-grained organizations become a viable option. It is demonstrated that the technique can be used to develop building blocks for both synchronous and asynchronous circuits, supporting the development of hybrid architectures such as globally asynchronous, locally synchronous.
Subjects	Circuits and Systems
Keyword(s)	asynchronous circuits parallel architectures reconfigurable architectures fine-grained approach globally asynchronous architectures hybrid architectures interconnect locally synchronous architectures polymorphic hardware platform reconfigurability spatial computing state element synchronous circuits undifferentiated logic cell vertical layout style
Copyright notice	© 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
ISBN	0-7695-1926-1

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