High performance extendable instruction set computing

Lee, H, Beckett, P and Appelbe, W 2001, 'High performance extendable instruction set computing', in G. Heiser (ed.) 6th Australasian Computer Systems Architecture Conference, Gold Coast, Australia, 29-30 January 2001, pp. 89-94.

Document type: Conference Paper
Collection: Conference Papers

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n2001000381.pdf Published version application/pdf 582.96KB
Title High performance extendable instruction set computing
Author(s) Lee, H
Beckett, P
Appelbe, W
Year 2001
Conference name Australasian Computer Systems Architecture Conference
Conference location Gold Coast, Australia
Conference dates 29-30 January 2001
Proceedings title 6th Australasian Computer Systems Architecture Conference
Editor(s) G. Heiser
Publisher IEEE
Place of publication Los Alamitos, USA
Start page 89
End page 94
Abstract In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset and immediate operands can be extended to 32 bits via the operation of an extension flag. The code density of the EISC instruction set and its memory transfer erformance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems. The compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations. This paper suggests a mechanism by which these dependencies might be removed in hardware.
Subjects Circuits and Systems
DOI - identifier 10.1109/ACAC.2001.903365
Copyright notice © 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
ISBN 0-7695-0954-1
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