A precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrodes retinal prosthesis

Chun, H, Tran, N, Yang, Y, Kavehei, O, Bai, S and Skafidas, S 2012, 'A precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrodes retinal prosthesis', in Michael C.K. Khoo (ed.) Proceedings of the 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, San Diego, United States, 28 August - 1 September 2012, pp. 3001-3004.


Document type: Conference Paper
Collection: Conference Papers

Title A precise charge balancing and compliance voltage monitoring stimulator front-end for 1024-electrodes retinal prosthesis
Author(s) Chun, H
Tran, N
Yang, Y
Kavehei, O
Bai, S
Skafidas, S
Year 2012
Conference name 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society
Conference location San Diego, United States
Conference dates 28 August - 1 September 2012
Proceedings title Proceedings of the 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society
Editor(s) Michael C.K. Khoo
Publisher IEEE
Place of publication Piscataway, United States
Start page 3001
End page 3004
Total pages 4
Abstract In this paper, we present a precise charge balancing and compliance voltage monitoring stimulator frontend for 1024-electrode retinal prosthesis. Our stimulator is based on current mode stimulation. To generate a precisely matched biphasic current pulse, a dynamic current copying technique is applied at the stimulator front-end. A compliance voltage monitoring circuitry is included at the stimulator frontend to detect if a voltage across electrode-tissue interface goes beyond a predefined compliance voltage. Simulation results show the mismatch of a biphasic current pulse (at a maximum stimulation current of 476μA) is less than 0.1%. Also, the stimulator issues alarm signals, when a voltage compliance occurs during stimulation due to high tissue impedance. Our stimulator is implemented using a 65nm low voltage (LV) CMOS process, which helps reducing implementation area and power consumption.
DOI - identifier 10.1109/EMBC.2012.6346595
Copyright notice © 2012 IEEE
ISBN 9781457717871
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