Area performance tradeoffs in NCL multipliers using two-dimensional pipelining

Kim, M, Kim, J and Beckett, P 2015, 'Area performance tradeoffs in NCL multipliers using two-dimensional pipelining', in 2015 International SoC Design Conference (ISOCC), Gyungju, South Korea, 2-5 Nov. 2015, pp. 125-126.


Document type: Conference Paper
Collection: Conference Papers

Title Area performance tradeoffs in NCL multipliers using two-dimensional pipelining
Author(s) Kim, M
Kim, J
Beckett, P
Year 2015
Conference name 2015 International SoC Design Conference (ISOCC)
Conference location Gyungju, South Korea
Conference dates 2-5 Nov. 2015
Proceedings title 2015 International SoC Design Conference (ISOCC)
Publisher IEEE
Place of publication USA
Start page 125
End page 126
Total pages 2
Abstract The natural pipelining behavior of Null Convention Logic (NCL) can often result in high speed data paths with fewer gate delays. However, the spanning completion detection and shared completeness path of the NCL handshaking signal may need very large completion detection gates that exhibit excessive fan-in, long propagation delays and high capacitance. Fine grained Two-Dimensional (2D) Pipelining for NCL circuits has been suggested as a potential solution. In this paper, we show a high throughput multiplier design based on 2D pipelining with NCL and compare it to equivalent non-pipelined and 1D pipelined case. We show an overall performance improvement of 260% in exchange for a similar area penalty.
Subjects Microelectronics and Integrated Circuits
Keyword(s) Arrays
Computers
Delays
Logic gates
Pipeline processing
Registers
Throughput
2D pipelining
Asynchronous logic
Multiplier
Null Convention Logic
Pipelining
Copyright notice © 2015 by IEEE
ISBN 9781467393089
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