• RMIT Australia
  • RMIT Global
  • RMIT Australia
  • RMIT Europe
  • RMIT Vietnam

• Students
• Alumni
• Staff

Research Repository

Back to Library

• Home
• Browse
• Search
• FAQs
• About
• Contact Us

Design and implementation of finite state machine decoders for phase disposition pulse width modulation of modular multilevel converters Teixeira, C, Sun, Y, Holmes, G and McGrath, B 2016, 'Design and implementation of finite state machine decoders for phase disposition pulse width modulation of modular multilevel converters', in Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE 2016), Milwaukee, United States, 18-22 September 2016, pp. 1-8. Document type: Conference Paper Collection: Conference Papers Attached Files Name Description MIMEType Size n2006070961.pdf Accepted Manuscript application/pdf 1.37MB Title Design and implementation of finite state machine decoders for phase disposition pulse width modulation of modular multilevel converters Author(s) Teixeira, C Sun, Y Holmes, G McGrath, B Year 2016 Conference name 2016 IEEE Energy Conversion Congress and Exposition (ECCE) Conference location Milwaukee, United States Conference dates 18-22 September 2016 Proceedings title Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE 2016) Publisher IEEE Place of publication United States Start page 1 End page 8 Total pages 8 Abstract It is well known that level shifted phase disposition pulse width modulation (PD-PWM) achieves the best possible three-phase line-to-line output voltage spectrum for multilevel converters. However the strategy does require post modulation signal decoding to optimally select between redundant switched states and to achieve an even distribution of commutation events across all switching devices. For modular multilevel converters (MMCs), PD-PWM involves firstly scheduling the individual module switching events of both arms as an integrated process to achieve optimal harmonic performance, and then selecting between redundant states to balance the individual module capacitor voltages, and to also minimise the phase leg high frequency circulating currents. This paper discusses the design and implementation of finite state machine PD-PWM post modulator decoders for MMCs to achieve these objectives. The proposed approach has been verified in simulation and then with experimental confirmation using a two module per arm MMC. Subjects Power and Energy Systems Engineering (excl. Renewable Power) Industrial Electronics DOI - identifier 10.1109/ECCE.2016.7855008 Copyright notice © 2016 IEEE ISBN 9781509007370 Related Links Link Description http://dx.doi.org/10.1109/ECCE.2016.7855008 Link to Published Version   Versions Version Filter Type Tue, 28 Feb 2017, 08:23:35 EST Wed, 21 Nov 2018, 10:26:31 EST Wed, 28 Nov 2018, 14:52:45 EST Filtered Full Citation counts:   Cited 0 times in Thomson Reuters Web of Science Article Cited 0 times in Scopus Article Altmetric details: Access Statistics: 146 Abstract Views, 41 File Downloads  -  Detailed Statistics Created: Tue, 28 Feb 2017, 08:21:00 EST by Catalyst Administrator