Design and simulation of a high performance rail-to-rail cmos op-amp at ±3v supply

Bhaskaran, M, Sriram, S, Stojcevski, A and Zayegh, A 2006, 'Design and simulation of a high performance rail-to-rail cmos op-amp at ±3v supply', in Proceedings of the Third IEEE International workshop on Electronic Design, Test and Applications (DELTA '06), Kuala Lumpur, Malaysia, 17-19 January 2006.


Document type: Conference Paper
Collection: Conference Papers

Title Design and simulation of a high performance rail-to-rail cmos op-amp at ±3v supply
Author(s) Bhaskaran, M
Sriram, S
Stojcevski, A
Zayegh, A
Year 2006
Conference name DELTA 06
Conference location Kuala Lumpur, Malaysia
Conference dates 17-19 January 2006
Proceedings title Proceedings of the Third IEEE International workshop on Electronic Design, Test and Applications (DELTA '06)
Publisher IEEE Computer Society
Place of publication Los Alamitos, United States
Abstract The paper discusses a CMOS operational amplifier at ± 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using Cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with Slew Rate of 49.24 V/µs, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.
Subjects Microelectronics and Integrated Circuits
Keyword(s) CMOS analogue integrated circuits
circuit simulation
integrated circuit design
operational amplifiers
25.44 mW
CMOS operational amplifier
bias current reduction
high performance op-amp
rail-to-rail op-amp
functional materials and microsystems
DOI - identifier 10.1109/DELTA.2006.30
Copyright notice © 2005 IEEE
ISBN 0-7695-2500-8
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