Clock-Less DFT-Less Test Strategy for Null Convention Logic

Nemati, N, Beckett, P, Reed, M and Fant, K 2018, 'Clock-Less DFT-Less Test Strategy for Null Convention Logic', IEEE Transactions on Emerging Topics in Computing, vol. 6, no. 4, pp. 460-473.


Document type: Journal Article
Collection: Journal Articles

Title Clock-Less DFT-Less Test Strategy for Null Convention Logic
Author(s) Nemati, N
Beckett, P
Reed, M
Fant, K
Year 2018
Journal name IEEE Transactions on Emerging Topics in Computing
Volume number 6
Issue number 4
Start page 460
End page 473
Total pages 14
Publisher IEEE
Abstract Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of I-DDQ (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I-DDQ testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I-DDQ test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clock-less, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I-DDQ test for
Subject Circuits and Systems
Keyword(s) Asynchronous circuits
automatic test pattern generation (ATPG) I-DDQ (quiescent current) test
delay insensitive circuits
null convention logic (NCL)
DOI - identifier 10.1109/TETC.2016.2593628
Copyright notice © 2016 IEEE. Translations and content mining are permitted for academic research only
ISSN 2168-6750
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