Hysteresis current regulation of voltage source inverters with constant switching frequency

Davoodnezhad, R 2014, Hysteresis current regulation of voltage source inverters with constant switching frequency, Doctor of Philosophy (PhD), Electrical and Computer Engineering, RMIT University.

Document type: Thesis
Collection: Theses

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Title Hysteresis current regulation of voltage source inverters with constant switching frequency
Author(s) Davoodnezhad, R
Year 2014
Abstract The thesis presents an integrated approach for constant frequency closed-loop hysteresis current control of a VSI. The proposed approach uses the fact that the switching frequency of a fixed-band hysteresis-controlled inverter varies according to the average load voltage. A novel technique is used to measure this average voltage by capturing transition times of the phase leg switching events, to avoid the frequency roll-off effects of using a low pass filter. The average voltage is then used to vary the hysteresis band in order to keep the VSI switching frequency constant. Next, a refinement is applied to the variable band to synchronise the zero-crossing of the current error to a fixed reference clock. The zero-crossing time is calculated by linearly interpolating between the captured switching transition times, to avoid the need for direct measurement of the zero-crossing event. This achieves a more robust and accurate synchronization process compared to current state-of-the-art time-based and deadbeat hysteresis controllers. For a three-phase VSI, the common mode current is subtracted from the phase leg current error that is calculated from three-phase leg gate signals. Further enhancements are then presented to extend the linear modulation range by 15%, to maintain excellent switching stability during excursions into overmodulation and to replace the third phase regulator with a fixed frequency directly modulated phase leg. The overall result is a two-level hysteresis current control approach with a harmonic performance that is similar to open-loop CSVM.

The average voltage calculation of the phase leg switched voltage then allows the integrated control concept to be applied to three-level three-phase multilevel topologies. Firstly, it allows the development of a three-level variable hysteresis band with band refinement similar to a two-level inverter. Secondly, it facilitates the development of a logic decoder based on the identification of the average voltage zero-crossings, so that only one hysteresis comparator is required per phase leg. A finite state machine is then developed to utilize the redundant switching states of the VSI similar to open-loop phase-shifted PWM. The control concept is then extended to suit a three-phase system by compensating for the common mode interacting current in a similar way as was done for two-level inverters. Further developments are then presented to synchronize the three-phase current errors to a fixed reference clock. The overall result is a three-level hysteresis current control approach that achieves a performance similar to open-loop phase disposition (PD) pulse width modulated three-phase multilevel inverter.
Degree Doctor of Philosophy (PhD)
Institution RMIT University
School, Department or Centre Electrical and Computer Engineering
Keyword(s) Non-linear current control
Two level hysteresis control
three level hysteresis control
multilevel hysteresis control
variable band
constant switching frequency
three phase hysteresis control
neutral point compensation
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Created: Thu, 06 Feb 2014, 10:58:25 EST by Brett Fenton
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