A software phase locked loop from theory to practice: TMS320C6000 DSP based implementation and analysis

Sithamparanathan, K 2006, 'A software phase locked loop from theory to practice: TMS320C6000 DSP based implementation and analysis', in Dr Johnson Agbinya (ed.) Proceedings of AusWireless conference 2006, Sydney, Australia, 13-16 March 2006, pp. 1-6.


Document type: Conference Paper
Collection: Conference Papers

Title A software phase locked loop from theory to practice: TMS320C6000 DSP based implementation and analysis
Author(s) Sithamparanathan, K
Year 2006
Conference name AusWireless conference 2006
Conference location Sydney, Australia
Conference dates 13-16 March 2006
Proceedings title Proceedings of AusWireless conference 2006
Editor(s) Dr Johnson Agbinya
Publisher University of Technology, Sydney
Place of publication Sydney, Australia
Start page 1
End page 6
Total pages 6
Abstract The study of phase locked loops (PLL) has been heavily treated in literature and most of the theoretical and the analytical results of such are verified using simulations. Here we provide a real-time implementation of a PLL on a digital signal processor (DSP) and analyse and verify the theoretical results associated with it on the implemented system. Such work takes us one step above from the traditional simulation and analysis of PLL to real-time implementation and analysis. The steady state and the acquisition of the PLL are analysed. Issues such as quantization errors are also discussed.
Subjects Wireless Communications
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