A complex-envelope based digital phase locked loop with an arctan phase detector implemented on FPGA and performance analysis

Sithamparanathan, K, Hashmi, O and Zheng, Q 2007, 'A complex-envelope based digital phase locked loop with an arctan phase detector implemented on FPGA and performance analysis', in Proceedings of 6th International Conference on Information, Communications & Signal Processing, Singapore, 10-13 December 2007, pp. 439-443.


Document type: Conference Paper
Collection: Conference Papers

Title A complex-envelope based digital phase locked loop with an arctan phase detector implemented on FPGA and performance analysis
Author(s) Sithamparanathan, K
Hashmi, O
Zheng, Q
Year 2007
Conference name 6th International Conference on Information, Communications & Signal Processing
Conference location Singapore
Conference dates 10-13 December 2007
Proceedings title Proceedings of 6th International Conference on Information, Communications & Signal Processing
Publisher IEEE
Place of publication New Jersey, United States
Start page 439
End page 443
Total pages 5
Abstract In this paper we present a Digital Phase Locked Loop (D-PLL), based on an arctan phase detector for complex signals, implemented on a Field Programmable Gate Array (FPGA) together with its performance analysis. The work is motivated by the requirement of signal synchronisation in Software Defined Radios (SDR) for high speed communication receivers. The theoretical model for the D-PLL and its corresponding implementation methodology on a Xillinx Virtex-IV FPGA are given in this paper. We also provide some test results and simulations results on the implemented system and verify them using the theoretical models.
Subjects Wireless Communications
Keyword(s) Arctan
CORDIC
D-PLL
FPGA
Phase detector
DOI - identifier 10.1109/ICICS.2007.4449626
Copyright notice © 2007 IEEE
ISBN 9781424409822
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