A novel low-power full-adder cell for low voltage

Navi, K, Maeen, M, Foroutan, V, Timarchi, S and Kavehei, O 2009, 'A novel low-power full-adder cell for low voltage', Integration: the V L S I journal, vol. 42, no. 4, pp. 457-467.


Document type: Journal Article
Collection: Journal Articles

Title A novel low-power full-adder cell for low voltage
Author(s) Navi, K
Maeen, M
Foroutan, V
Timarchi, S
Kavehei, O
Year 2009
Journal name Integration: the V L S I journal
Volume number 42
Issue number 4
Start page 457
End page 467
Total pages 11
Publisher Elsevier BV
Abstract This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.
Keyword(s) Full adder
Majority function
Low power
Very large-scale integrated (VLSI) circuit
Performance analysis
Static CMOS inverter
MOSCAP
DOI - identifier 10.1016/j.vlsi.2009.02.001
Copyright notice © 2009 Elsevier B.V. All rights reserved.
ISSN 0167-9260
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